Roger Beep - tone waveform development
This article outlines the design of the synthesised low distortion sine wave in the Roger Beep circuit. The wave is to be synthesised with a low pin count MCU with only three digital pins available for the purpose.
The objective is to design a stepped representation of a sinusoidal wave that can be easily created from three digital output pins, and that with simple filtering, will result in a low distortion sinusoid.
The wave is normalised in this analysis to have period of 2π and amplitude 1. The stepped representation will have five voltage levels: +1. +v, 0, -v, and -1. The design exercise is to find suitable values for α, β, and v. The chip maximum clock rate restricts values α and β to 256 discrete steps. See Fig 1.
Fourier's theorem states that this stepped waveform can be represented as a Fourier series, a constant and an infinite series of sin and cos
Exploiting the symmetry, the terms a0, all an for even n, and all bn will be zero.
Fig 2 shows the development of the Fourier series coefficients an, in terms of α, β, and v. (The Fourier analysis is over a quarter cycle exploiting quarter cycle symmetry.)
Note that the series converges (ie, the higher order terms smaller, the n in the denominator.)
Fourier analysis will show that the waveform has no DC component, no no even harmonics, and odd harmonics that diminish.
If by optimisation of α, β, and v, the magnitude of the low order harmonics can be minimised, it makes the filtering task easier because the filter does not need a sharp cut-off response.
A spreadsheet was built to calculate and plot the magnitude of the an terms against v for given values of α and β. A little juggling of α and &beta found values that gave a minimum total power in the the a3, a5 and a7 terms, and the associated value v. Fig 3 shows the plots against v for the optimal values of α and &beta, optimal value of v around 0.62 gives minimum total third, fifth and seventh harmonics. The ninth and eleventh harmonics are off scale (0.12 and 0.08 respectively) and will need filtering for further reduction.
The result of optimisation of α, β, and v is that total power in the third, fifth and seventh harmonic is 42dB down, so a simple RC filter will reduce the higher order harmonics sufficiently.
A circuit was designed to implement a simple ADC and single section RC filter to produce a sine wave with distortion below 2%.
Fig 3 shows the filtered DAC output. Measurement with a Distortion Analyser is less than 2%. Distortion is even lower after it has passed through the SSB generation process in a transceiver, measured distortion from a TS2000 TX MONI output was 0.7%.
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