PllLdr application - AD9833

This article describes an application of PllLdr to an AD9833 DDS.

The target DDS module was purchased on eBay for about A$3 including post. The module contains the AD9833 DDS chip and a 25MHz crystal reference.

Fig 1:

Fig 1 shows the prototype module. The DDS module which is fitted with header pins was accommodated on a small piece of Veroboard with a PllLdr hosted on an ATtiny24A, some DIP switches for selection of 1 of 16 frequencies from the channel memory in PllLdr EEPROM and an ISP socket.

Note that there is no adjustment of the frequency of the 125MHz crystal, so the factor loaded into the AD9850 must be adjusted to compensate for crystal error. In my case the crystal was 4kHz low (at 125MHz) so 32ppm must be added to the factor loaded into the AD9850. Short term stability is reasonable for a non-ovened crystal, on random observations over a day the frequency was within 100Hz at 7Mhz with an un-aged crystal.

{
"ver":"02",
"rbo":"",
"options":["8120","0000"],
"regs":[
["210062B74DFD2000"],
["21006AB34DCF2000"],
["21004E224DD62000"],
["210071904DDC2000"],
["210054FE4DE32000"],
["2100786C4DE92000"],
["21005BDA4DF02000"],
["21007F484DF62000"]
]
}

Above is an example EEPROM configuration file for a 8 channel transmitter.

SK. QRSS keying is applied to pin 2 of the chip. Note that the factors used include calibration adjustments for this particular crystal.

Current consumption on 5V supply is about 10mA.

Links

• PllLdr

Changes