PllLdr application - AD9850/51 300Bd FSK

A work in progress...

Bruce, VK2ZZM, floated a possible project for a simple 30m mobile transmitter for APRS application.

The key specifications for the exciter section are:

A possible solution


The AD9850/51 DDS chips offer the basis of a possible solution for the exciter.

Fig 1:

Fig 1 shows the prototype used for testing. The AD9850/51 daughter boards are available on eBay for $12-$20 including post. The prototype pictured is an AD9850 with 125MHz local oscillator, configured to testing the modulation scheme. Another daughter board with AD9851 and 30MHz clock has also been used in testing.

The design concept is to use the PllLdr chip running standard firmware for the DDS controller, and to feed the incoming 300Bd telegraphy to the LSB of the PllLder frequency select pins. Although the prototype uses an ATtiny24A, an ATtiny25 is quite adequate to the end application, it just one frequency select pin available, but that is sufficient.

Spectral distribution

To explore the spectral implications, a number of experiments were conducted using a TS2000 receiver in SSB model (basically as a linear down converter from 30m to audio frequencies), and analysing the audio output spectral response with Spectrogram. The test was conducted using the production PllLdr firmware, and the no-debounce configuration option selected to permit maximum keying speed.

For this application with deviation (D) of 100Hz, bit rate (R) of 300bps, from (ITU 1990) the Necessary Bandwidth for Binary FSK under random traffic is given from: M=B/2=300/2=150, Bn=2M+2DK where K=1.2, Bn=2*300+2*100*1.2=540Hz.

Fig 2:

Fig 2 shows the demodulated spectral content of the DDS modulated by a 300Bd isochronous test signal (where every element alternates). An isochronous input is a worst case signal for bandwidth, the Power Spectrum Density (PSD) distribution will be wider than with random traffic. In this case, more than 99% of the power is contained within 600Hz, Occupied Bandwidth is 600Hz, which captures the carrier and the first two sidebands on each side.

The DDS /  controller changes frequency phase synchronously or at a zero crossing. This gives lower bandwidth than schemes that switch between two oscillators, or that sinusoidally shift a VCO from MARK to SPACE etc. A number of options with stepwise approximation of raised cosine and Gauss error function transitions was tried, but they did not significantly reduce necessary bandwidth.

Frequency accuracy / stability

The required frequency accuracy of 1e-6 could be obtained from a OCXO or TXCXO. Custom oscillators are expensive, so use of an off the shelf oscillator is preferable. Ebay is a potential source of low cost oscillators.

Using an AD9850 to generate 10.15MHz, the oscillator needs to be about 30MHz or higher. The exact frequency is not critically important, it is factored out in the calculation of the DDS register contents.

Another option is an AD9851 which has an internal x6 multiplier, and could be used to cover the requirement with an oscillator from about 5Mhz (including high accuracy sources such as GPSDO, Rubidium etc). Importantly, an AD9851 opens up the opportunity to use low cost 1ppm TCXOs in the 10−30MHz range that are readily available on eBay.

So, a workable solution might be a TCXO at around 25MHz, AD9851, frequency shift keyed by using PllLdr with MARK and SPACE frequencies selected by the telegraphy applied to frequency select bit 0.

Example workup

A search of eBay for "TCXO" listed a large number of oscillators in the 20 - 30MHz range with 1ppm accuracy.

Fig 3:

Fig 3 shows an example, this one at 24.576MHz. Using the 6x multiplier, the register contents are calculated as per the datasheet.

Fig 4:

Fig 4 shows the example configuration data. An adjustment to these values could be made based on the measured reference frequency.

References / links

Cohen, D. 1985. NTIA report 84-168, necessary bandwidth and spectral properties of digital modulation. US Dept of Commerce.

ITU. 1990. Radio Regulations. Geneva: ITU.



Version Date Description
1.01 08/01/2012 Initial.
1.02 30/01/2012 Major rework.

© Copyright: Owen Duffy 1995, 2021. All rights reserved. Disclaimer.