An experimental CPLD based PLL

Design concept

Features

• Integer N synthesis;
• CPLD based;
• programmable dividers;
• jumperless or near jumperless configuration;
• exploitation of non-volatile memory for operating parameters;
• capability to lock a free running VCO or crystal oscillator at up to at least 100MHz without prescalers.
• flexible;
• low cost;

The device selected is an Altera MAX II CPLD which not only stores its configuration on internal flash memory, but also contains 8kb of flash memory for user use (more on this later).

Fig 1: Block diagram

The CPLD incorporates:

• programmable dividers for the VCO and REF inputs,
• an XOR based phase detector (PD1);
• a phase frequency detector (PD2); and
• facility to load the dividers from one of sixteen data pairs in User Flash Memory (on the fly).

The optional frequency select input can be used as:

• a 4 bit binary address of N and R divide ratios; or
• as one of four (or one of four + none of four) to select one of four or five divide ratios from a simpler selector switch.

The frequency selection scheme could be used to provide options for a LO for different IF frequencies (eg 144, 432MHz) or different bands (eg 2304, 2400MHz). If the frequency selection is changed, the new data pair is fetched from UFM and used without any other intervention.

Initial design is that the REF divider ratio has a range of 1 to 128 in increments of 1, and VCO divider ratio has a range of 1 to 63384 in increments of 1. These could be expanded easily, but driving comparator frequency down increases phase noise in the system, and the maximum input frequency is reduced slowly.

The phase frequency detector (PD2) has two charge pump outputs that drive a charge integrator which provides the loop filter. The design allows low loop bandwidth without restricting VCO lock range. The logic design provides for a very small overlap between the UP and DOWN charge pumps to eliminate a dead zone around the crossover point. An XOR phase detector (PD1) is also provided.

Problems to be solved

Post production UFM update

The hope was to be able to program the CPLD UFM post production using Altera's standard programmer with USB Blaster or Byte Blaster, from a Intel hex file of the divider ratio pairs.

The preferred approach would be to use a Jam Composer to convert the hex file into a Jam STAPL file to be played by Quartus programmer.

Fig 2: Data storage flow chart

Fig 2 is from an Altera preliminary publication dated 2004. The "UFM HEX to Jam Utility" element does not appear to exist. Altera say in that document "Small capacity, non-volatile memory is commonly used in storing manufacturing data (e.g., manufacturer’s IDs, serial numbers). This data is important in differentiating products, inventory referencing, and storing test results during manufacturing. The MAX® II user flash memory (UFM) is ideal for storing manufacturing data instead of using a separate low-density, non-volatile memory device. This solution creates a low-cost, portable medium for storing and controlling access to information. You can read and write manufacturing data using the IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface." I couldn't say it any better, but they have not provided the glue.

Altera's white paper entitled "Low-Cost Integration of Serial EEPROMs and Flash Memory Devices" dated March 2008 plows on espousing the virtues of the CPLD as a replacement for conventional EEPROMs, but doesn't address the gap identified above.

I have raised the issue in a service request to Altera, but I was told to create a .pof file for the whole project (CFM and UFM) using Quartus II. This is not a solution to the need to be able to allow field creation a UFM update without distributing the design IP.

The problems with post production update of the UFM are so significant that the work around is to not use UFM and use a 24LC08 EEPROM. A separate I²C programming interface to the EEPROM could be provided, or it could be socketed for removal and programming with an inexpensive programmer that will read a hex file. This requires development of an I²C interface on the CPLD, not a huge task.

MAX II family flash endurance

Specifications suggest a maximum endurance of 100 erase cycles, and no minimum or typical value. This falls well short of the 10⁷ expected of EEPROM. Note that this application does not write flash during normal operation, it is only written by an external update.

Possible extensions

Ideas that may or may not be implemented:

• two REF inputs, one for an onboard crystal oscillator, and a second for an external reference (eg GPSDO);
• autoswitching between two REFs';
• selection of divider ratios based on selected REF;
• muting the PD outputs when the frequency is being changed;
• lock indicator;
• software application to generate the hex data from a list of frequencies;

Status

The CPLD design has been created and tested without the VCO.

Fig 3: Prototype

Fig 3 shows the digital prototype, in this case an inexpensive development board purchased on Ebay. The VCO signal is from the on board 33MHz crystal oscillator and the REF signal is from a 1MHz signal generator.

The task is now to build a VCO, loop amplifier / integrator, and VCO and REF level converter, and test the system.

Final

After exhaustive searching for a utility program to create a JAM file for UFM from a MIF or HEX data file, I have abandoned the project.

What appeared to be an elegant project for a jumperless flexible PLL based on the CPLD with a minimum of other chips falls on the availablility of a convenient stand alone method of updating UFM post manufacture. A GUI utility was planned to build a hex configuration from the user's requirements, run the conversion to JAM behind the GUI, and run a JAM player to program the chip's UFM using a JTAG interface.

Alter described a HEX/JAM conversion utility in an earlier handbook for the MAX II, one can only assume that they recognised the potential but there is some defect in the chip design that prevents effective use. Perhaps Altera's guaranteed limit of just 100 flash memory write cycles is the reason they don't want people using UFM in that way... bit hard to fathom when Xilinx guarantee at least 10,000 flash write cycles.

Other methods of rewriting UFM using i2C etc were explored, but they are unwieldy in that they use hundreds of LEs, requiring a bigger, more expensive CPLD than otherwise needed.

A search for a competitive device with user post production programmable configuration parameters turned up nothing, the concept might just be ahead of CPLD development at this time.

To salvage something from the work, I may modify the design to use an external EEPROM (eg 25LC16) for the divider lookup tables, reserving the CPLD for the dividers and phase frequency detector (and of course some 100 or so LEs to implement the read of the EEPROM). To avoid multi master i2C support in the CPLD, it will probably be necessary to program the EEPROM in a stand alone programmer.

The last word

Having looked at modern synthesiser technology, I have abandoned the concept described in this article. There appears to be better PLL devices complete with integral VCO, or those designed to work with an external VCO module possibly with internal prescaler.

One of the factors killing the CPLD was that very low endurance limit for the UFM, just 100 writes. EEPROM in most microcontrollers or standalone EEPROM chips have endurance limits of 100,000 writes.

Most of those synthesisers have some type of internal loop optimisation processes that are probably better than the simple phase frequency detector implemented in this project. These synthesisers offer a great deal of flexibility in a simpler package and are usually configured using a simple SPI interface from typically, a MCU with stored sets of configuration data. The project MCU to load PLL configuration registers is such a controller.

Changes

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