# Digital display for half wave detector with cubic spline interpolation – part 4

Digital display for half wave detector with cubic spline interpolation – part 1 and following articles laid out the design concepts of a power meter display.

Digital display for half wave detector with cubic spline interpolation – part 2 described a simple cubic spline interpolation model.

This article examines the problem a little deeper to arrive at an improved solution. The chart above compares the response of an ideal peak detector (cyan) with an LTSPICE simulation of a BAT46 with 57kΩ load (orange x). Whilst the simulation approaches the ideal at peak RF voltage Vp greater than 3V, it departs greatly at very low Vp.

Let's recall that $$P_{rf}=\frac{V_p^2}{2R_l}$$, and that for an ideal diode half wave detector, $$V_{dc}=V_p$$. So at high Vp (where the diode response approaches ideal), $$P_{rf} \propto V_{dc}^2$$, and the second order curve fit use in Digital display for QRP labs 20W dummy load – part 1 can give a good approximation in that region with some correction of the non-linearity down to Vp=1V or so.

Recognising that the ideal response is a straight line in the log domain, ie $$\log P_{rf} \propto \log V_p$$, an alternative approach that might yield better range is a cubic spline interpolation of log Prf vs log Vp. The above chart is of points from the LTSPICE simulation and eight points with smoothed curve between them. Note that visually it is in the log domain, the scales are log/log, and the smoothed curve gives a good idea of how a log cubic spline interpolation will play.

Applying that data to the BAT46 detector with 56k/1k divider, a cubic spline model was created. Above is a screenshot of the log cubic spline fit and the derived array definition in C++. Above is a comparison of LTSPICE dataset, basis points for the log cubic spline model, and the interpolation. Above is a screenshot of the EEPROM map including some additional variables for calibration improvement.

This approach has been tested and performs well.

## Next

Next step is to evaluation ADC noise on some more dev board candidates. The behaviour of the external ADS1115 ADC will remain the best, but there is some convenience in using an on-chip ADC if it suits an application.

A work in progress..