A simple generic Simsmith model of a linear push-pull Class B broadband HF power amplifier

This article outlines a Simsmith model developed to explore / confirm behavior of some linear Class B push-pull HF broadband power amplifiers.

The design is for a system power output of about 80W on a 24V supply, it is a combination that should work with practical system components with good efficiency.

Above is a first step, an estimate of an initial load line for the PA. The calculator is written in valve terms, but is quite applicable to this scenario.

Let’s talk in terms of MOSFET devices. So, we expect that the drain to drain load needs to be around 12.6Ω, that is close to 50/4=12.5Ω and would suit a 1:2 turns ratio broadband transformer, so we will base the Smith chart on Zo=12.5Ω.

The article assumes the reader has a good understanding of these type of amplifiers.

This article assumes familiarity with Simsmith, including its right to left signal flow, and concepts of complex numbers, impedance, admittance, circuit analysis, transformer equivalent circuits etc.


The model is a simple approximation of the behavior of the PA and makes some assumptions to make a very complex system into a simpler approximation that leads to an understanding of the main influences on system power out.


The model assumes ideal Class B operation of an ideally linear active device with conduction angle 180°. The conduction angle in Class AB is typically so close to 180° to make little difference to the calculated result, insignificant in terms of other uncertainty.


The model assumes an ideal linear transfer characteristic. The error of this assumption is small in estimating power output at the fundamental, but relevant to IMD / harmonic content… which is outside the scope of this model.

That said, the real test of linearity is an Intermodulation Distortion (IMD) test, statistics like 1dB compression power (P1dB) are pretty weak. The analysis presented hear avoids voltage or current saturation, slightly higher power might be obtainable at acceptable IMD figures.

Model overview

The source element G

The nature of the active device, whether transistor or FET is that with a given level of drive, it tends to produce a collector or drain current independent of load impedance. Constraints on output power in linear operation are:

  • the available voltage swing (approximately supply voltage V+ less saturation voltage (Vsat) of the active device); and
  • maximum peak current available.

Generator model – V_ property

With adjustable drive available (eg using ALC), we can consider that the output device is a nearly ideal voltage source Vmax=Vdd-Vsat able to supply current up to some Imax.

In the Simsmith model, that has been specified in the Zo sub element as

Vdd; Vsat; Imax; absV(Min(Vmax*2^-0.5,Mag(Zin)*Imax*2^-0.5));

where the first three items are declarations of variables so they appear first in the list below. The important part is that it sets the source G to a RMS voltage that is the lesser of \(\frac{V_{max}}{\sqrt2}\) and \(\frac{|Z|I_{max}}{\sqrt2}\). Don’t be confused by absV, it does not set the source absolute voltage or amplitude, but the RMS voltage.

If you have notions of an idealised Thevenin or Norton source, they are not a good fit to this design problem.

Plt property

The Plt property of G specifies some calcs and plots.

Plot("CoreLoss (Wc)",Core.R1.p,"Wc",y1);
Plot("Dissipation (W)",Vdd*Idc-G.P,"PWR");
Plot("Efficiency %",efficiency,"Eff",y2);

Vmax is calculated from Vdd and Vsat, and Idc is calculated from G.I using the factor for ideal push-pull Class B operation. Two plots are specified, one of core loss and one of dissipation of the active devices being the difference between DC input power and RF output power. Active device efficiency is also calculated in %.

Above is an example set of plots for a contrived scenario to show departures from ideal PA behavior. There is a distinct roll-off below about 3MHz and a sharp change around 1MHz, and a broad efficiency roll-off above about 10MHz another sharp change in power out around 26MHz. We will discuss the cause of these later.

C2 element

C2 models the shunt capacitance at the drain or collector of the active devices. This is an average approximation of what is actually a capacitance that varies instantaneously with voltage.

Tfmr element

The Tfmr element models a transformer with a lossless ferrite core, it assumes very high flux coupling factor (which you can tweak). It is used with the Core element which has precedence setting some of the values.

(The model assumes that k is independent of frequency which is not strictly correct, but for medium to high µ cores, measurement suggests it is a fairly good assumption.)

Core element

The core element models the ferrite transformer core, and feeds the Tfmr with key values.

Above is the schematic of the Core element.

The core element models the ferrite core referred to the secondary side as a shunt admittance Ym. The susceptance and turns ratio are used to calculate the primary and secondary inductances of the Tfmr element, and the conductance creates a shunt element to approximate the core loss of the transformer referred to the secondary (LHS). It precedes Tfmr so that it sets Tfmr values prior to execution of Tfmr.

Below is the content of the Core element code.

//Core model
//Calculates magnetising admittance from mu data.
//Updates Tfmr Hl, Hr.
$data=file[]; // core mu

The input values are:

  • file: a csv file of complex permeability vs frequency;
  • aol: core geometry as \(\int \frac{area}{length}\);
  • Ns: number of turns on transformer secondary (primary is 1t);
  • cores: number of cores in cascade;
  • Cse: equivalent shunt capacitance.

C1 element

The C1 element models the Tfmr self resonance as an equivalent shunt capacitance.

L element

The L element is the nominal load, for most cases this will be 50+j0Ω. You can change it to observe the sensitivity of the design to variations in load impedance.

Analysis of the example scenario

The example scenario is contrived to exhibit some departures from ideal for the purpose of discussion.

Mid band – 5MHz

Above is a Smith chart of the impedance seen by source G normalised to Zo=12.5Ω. At O, freq=5MHz, it is pretty close to the target 12.5Ω. Power out is 84.5W (remember this should be followed by a LPF), efficiency is 75%, close to the theoretical efficiency of an ideal Class B stage.

Core loss is around 15W which is quite high. The design needs lower core loss.

Efficiency roll-off below 3MHz

Efficiency rolls off below 3MHz due to increasing core loss, magnetising admittance is too high. The design needs lower core loss, first point would be to address the core selection, cross section, number of cascaded cores, and material characteristics. Change the cores value and observe the result.

Sharp change in power out near 1MHz

The sharp change in power output near 1MHz is due to current saturation, the active device cannot produce the current required to drive the load with the growing magnetising admittance. Increasing MOSFET size and drive can solve this, but that does not solve the attendant efficiency problem.

Efficiency roll-off above 10MHz

Efficiency roll-off above 10MHz id due mainly to the increasing effect of C2, but flux leakage in Tfmr contributes also. Fix this by choosing MOSFETs with lower capacitance, and making sure the transformer has low flux leakage (high permeability, structure).

Sharp change in power out near 26MHz

The sharp change in power out near 26MHz is again due to current saturation.

Core loss

Core loss varies with the magnetising current and depends on core characteristics including the frequency dependent complex permeability. Select material and geometry to improve core loss.

Efficiency summary

Efficiency is degraded whenever the MOSFETs are not operating at fully voltage swing, so presentation of low load impedance might allow acceptable output power at acceptable IMD, but at degraded efficiency. It is worth measuring efficiency as an indicator of correct setup of the stage.

If you design for rated power into a load impedance with some tolerance, eg 60+j0Ω, that will result in reduced efficiency with a 55+j0Ω load. That is just part of the cost of a tolerant design so that half the units coming off the production line don’t fail to make rated power. In the same vein, the MOSFETs need to be able to drive a 45+j0Ω load. The Simsmith model allows exploring these variations.

A better PA

Above is an overview of the model applied to a commonly eBay listed nominal 70W Chinese PA. Yes, it falls short of the advertised 70W… but the fine print says that is on 16V… so try it.

But overall, the expected performance is quite good from 1.5-30MHz, and core loss is very low. (Note this core loss is based on VK1EA’s measurement of a single core, there is no assurance the cores used in products sold are of the same type.)

Reality check

The model will often predict lower power than some products claim. It is likely that they depend on driving the PA into saturation to achieve their stated power, causing degraded IMD performance (rarely stated).


The model provides a framework for exploring the second stage of a design process. At the end of the day, testing some prototypes is necessary to complete a design.

RfBPaSs.zip contains the two Simsmith v18.1g model files and their dependent csv files. The component files are available on github where updates will be posted. They are offered for study without any warranty.