AD9833 / PllLdr checkout

PllLdr is a generic microcontroller to load a PLL chip’s configuration registers using SPI. SPI is used by many PLL and DDS chips, data format and content varies from chip to chip.

This article documents checkout on an ADF9833 DDS chip.

The test was made on an inexpensive module purchased on eBay for about A$3 posted. This board has a 25MHz clock oscillator, but be aware they are sold with other frequencies as well, and is usable to about 40% of the clock frequency.

Above is the test board. It does not contain any form of output filtering, it really is bare bones.

Though the purpose of the test is primarily to test the SPI register load.

Above is the AS9830 module in the PllLdr test jig with power, logic analyser and programmer connections.

A json description of the data structure for PllLdr follows, only one slot is configured. The configuration puts the AD9833 into reset, reloads the two halves of a frequency register, and releases the reset condition.

//JSON syntax does not provide comments, filter this file through jsmin to
//strip comments
/*************************************************
EEPROM data file for AD9833 for lunchbox radio - low side osc
Owen Duffy 20200612
0: 7.115
1: 7.045
2: 7.055
3: 7.065
4: 7.075
5: 7.085
6: 7.095
7: 7.105
*************************************************/
//options: invert sel, invert SCK, 1/8
{
"ver":"02",
"rbo":"",
"options":["8120","0000"],
"regs":[
  ["210062B74DFD2000"],
  ["21006AB34DCF2000"],
  ["21004E224DD62000"],
  ["210071904DDC2000"],
  ["210054FE4DE32000"],
  ["2100786C4DE92000"],
  ["21005BDA4DF02000"],
  ["21007F484DF62000"]
]
}

Registers are loaded MSB first (differently to a lot of other AD synthesiser chips), and SPI mode 2. The 16 bit registers can be streamed in a single SPI transaction.

Above is a logic trace of the SPI transaction. It takes about 100µs + 8 output cycles to do a frequency change, so at 7MHz, that is as good as 100µs.

Above is a map of the EEPROM for this example configuration.