VU3SQM offers an interesting directional coupler based on a Sontheimer coupler, and using AD8307 power sensing for a nominally HF coupler. I must say that I am not a fan of Sontheimer couplers… but that is what the board uses.
This article lays out a preliminary design review to assist in selection of appropriate toroids, and ordering of the needed parts.
Above, the top side of a PCB.
Above, the schematic of the coupler.
A quick walk through of the design
The AD8307 is designed for a maximum input voltage equivalent to 17dBm (1.58V in 50Ω).
The attenuator between transformers and AD8307 has a voltage division of 24/(127+24)=0.159 or 1/6.29. (Zin of the AD8307 >> 24Ω, so it is insignificant.)
The transformers have a nominal voltage ratio of 30:1 and vice versa.
So, the input power in a matched system for FSD of the AD8307 (17dBm) is given as Vin=1.58*6.29/2*30=149.1V, and Pin=149.1^2/50=444W (56.47dBm). AD8307 calibration factor is 39.5dB. With Pfwd=50dBm, the AD8307 should receive 10.5dBm and the output voltage at nominal intercept should be (10.5–84)*0.025=2.36V. There is no hardware adjustment for intercept calibration, so some variation can be expected.
The 0.5W 150Ω resistors have a maximum voltage capability of (0.5*150)^0.5=5.477V, and so Vin<164V which corresponds to 164^2/50=538W
The response of the AD8307 is poorer in the top 3dB, so linearity is best up to about 200W input to the coupler, but continuous power rating is 538W (though beyond FSD).
The originally specified cores are a little on the shy side, so I will select a better suited core.
The core chosen is a Fairrite 2643540102, they are readily available in Australia for modest price. They are larger than the aperture in the board, so they will stand above the board (which has certain advantages and is the common practice.) The core should accommodate 30t of 0.5mm enameled wire.
Above is a calculation of expected magnetising admittance at 1.8MHz.
Above is a calculation of InsertionVSWR due to the shunt transformer alone on a 50Ω load.
Expected core efficiency is 0.02/0.0200227=99.9%, core loss is 0.113% (0.55W @ 500W input) or 0.005dB.
It is quite good, measurement will tell whether it is sufficiently flat for the intended range to 30MHz.
Intention is to make a PEP and ‘true’ average power indicating digital display.
That will require some analogue signal processing of the AD8307 output, (a peak hold stage, and a averaging filter), and possibly a high resolution I2C ADC built into the coupler box, and a remote display with LCD or OLED display.
The AD8307 has a nominal range of about 85dB. This range might be a little ambitious considering ADC limitations.
ADC resolution is key to instrument range for a given resolution.
Let’s say we want to measure ReturnLoss to 1dB resolution, we must measure Pfwd and Pref to 0.5dB resolution.
0.5dB resolution requires a minimum ADC count of ceiling(1/(10^(0.5/20)-1))=17.
If we choose a 12bit ADC, it has 2^16=4096 steps, and after allowing a minimum count of 17, it has a range of 4096/17=240 steps.
If the ADC FSD is 444W, then minimum power measurable Pmin to 0.5dB resolution is 444/240^2=0.0077W.
Similar calculations for 14, 12 and 10bit ADC yield Pmin= 4.7e-4, 0.93, 14.8W respectively.
If we use a 12bit ADC, and considered a load with VSWR=1.2 and Prev=0.0077W, Pfwd would be 0.93W, so it should measure VSWR of 1.2 or more for Pfwd down to just 0.93W.
At this point, most of the PCB parts have been ordered, and some RG400 cables with N panel jacks to connect from PCB to panel.
… more as it unfolds…