A NanoVNA was configured with a SMA tee connected to Port 1 and a good 50Ω termination connected to the branch port, see the pic below. The left hand side of the tee becomes the new Port 1 interface, and by virtue of the additional 50Ω shunt termination, if the native Port 1 was indeed well represented by a Thevenin equivalent circuit with Zs close to 50+j0, the Thevenin source impedance is now closer to half that, Zs close to 25+j0.

Some would calculate this mismatch as causing a mismatch loss of 0.512dB that is additional loss in the s21 path.

Above is the test setup. The NanoVNA was SOLT calibrated with cal parts attached to the left hand side of the tee and the 200mm coax jumper from that point to Port 2.

On completion of the SOLT, the s11 traces for SOL were verified, as was the S21 (0dB) trace with the coax jumper.

A good 10dB attenuator was then connected inline (at the Port 2 connector) and s21 measured.

Above is a screenshot from the NanoVNA, |s21| is -9.97dB, quite close to the expected -10dB.

Above is a capture from NanoVNA-APP of the same scenario, again using the stored VNA calibration. The departure is tiny, and does not hint for a moment a source mismatch loss of 0.5dB that was not corrected in the calibration process.

Note that properly calibrated, the NanoVNA will capture the departure of a sample of nominal 50Ω transmission line from exactly 50+j0Ω, and that will show up in |S21| measurements even if Port 2 was exactly 50+j0Ω.

Readers might not be too surprised to find that there is at least one reflection type antenna analyser that has quite a low source impedance, source matching is not an issue with the forward and reflected waves are measured and calculations base on both.

None of this is to suggest that mismatch at Port 2 is corrected in the NanoVNA’s own calibration process. That remains a source of error in measurements that depend on Port 2 match, eg the very popular s21 series through impedance measurement technique.

]]>This was a mod I devised prior to the v3.4 hardware change, it is not identical to that change as it preceded it, but it works fine on v3.3 hardware and may work on earlier versions.

The mod calls for replacing R5 with a 1k (1402) and running a short jumper from the T terminal of the jog switch to the un-grounded end of R6.

To use it, hold the jog switch in and turn the nanoVNA on.

Above a pic of the mod. It is a simple mod, but very fine soldering so it might not be within everyone’s capability.

]]>The coupler was purchased as an assembled module as pictured above.

It is a Sontheimer coupler and uses AD8307 logarithmic detectors in the FWD and REF channels.

The manufacturer publishes performance information not often published for such things.

From the above data, we can plan a digital display based on conversion of each of the RWD and REF detector output voltages.

As a first step, we can calculate the intercept and slope used to convert those voltages initially to dBm. Taking slope to average 0.0266V/dB and given 5W producing 1.925V out, we can calculate coefficients and write \(P_{dBm}=-35.4+\frac{V}{0.0266}\), and this would result in an output voltage from 0 to 2.7V.

Now the intended ADC will have a full scale deflection (FSD) around 1V, two options are being considered:

- SAMD21 M0 with Vref=1.0V; and
- ATmega328P with Vref=1.1V.

Low cost hardware is readily available in the form of Nano Zero (or similar such as above), and Arduino Nano boards.

So, using a 10bit ADC (quite sufficient resolution for this application), we get 1024 steps and it would suit us if the AD3807 had a slope of 10mv/dB so a 100dB range used most of the ADC’s FSD.

The diagram above shows the output stage of the AD8307 is a 2µA/dB current mirror and 12500Ω internal load. If we shunt that load with an external load resistor of appropriate value, we can get sensitivity to 10mV/dB.

Above is an extract from a spreadsheet which calculates the preferred external load resistor is 8200Ω for a slope of 9.9mV/dB.

The spreadsheet goes on to calculate the slope in terms of ADC count C, and it is 0.9861dB/C.

So the initial calculation in firmware is \(P_{dBm}=-35.4+0.09861 C\). These calibration coefficients for each of the FWD and REF detectors will be stored in EEPROM, so firmware does not contain the calibration coefficients in code.

The next step is to build a prototype and measure it to make final calibration adjustments.

Above is a plot of log conformance of the AD8307 from the datasheet. It would seem that the two pink spots are good candidates for a two point calibration, lets choose -48 and -6dBm equivalent at the AD8307 input which equates to 0.6 and 42.6dBm into the coupler.

So let’s say we measure a prototype detector (both FWD and REF must be done), and get actual vs input, we can calculate the corrected calibration coefficients.

Above is an example calculation, the new coefficients would then be stored in EEPROM.

A work in progress..

]]>The low frequency range is specified as 1.8-160MHz.

This project is for an external digital display to suit the low frequency band of the W560. Whilst this project is for a specific meter, the techniques are applicable more widely.

Above is the schematic of the W560. A 6.5mm TRS jack was added to the back panel, and the T and R connected to the F and R outputs of the low range sensor, bypassing all of the existing display circuitry. It appears that the equivalent source impedance of this connection is quite high and may need buffering.

The question is how the DC output voltage Vo and forward power P are related.

A naive answer might be that \(P \propto V_o^2\). A common proposition is that \(P \propto (V_o+V_{diode})^2\) where V_{diode} is say 0.2V for a germanium diode.

Let’s discover what that relationship is by measurement of the real wattmeter, the W560. A series of measurements were made to explore the relationship between the DC output voltage Vo and forward power P.

Above is a plot of the measurements from 0 to 200W.

Above is a plot of three curve fits:

- a simple square law fit: \(P=2.089*Vo**2\) (** is an exponentiation operator);
- a simple square law with diode offset fit: \(P=-1.80e-07+2.089*(Vo+-0.000294)**2\); and
- a full second order polynomial: \(P=1.026e-18+0.883*Vo+1.89*Vo**2\).

The first and second curves are nearly coincident.

Note that the diode offset voltage found by the second curve fit process was a tiny value, and actually of the opposite sign to the common explanation, and suggests the diode offset model often proposed is weak.

In the last case, the first term (Y intercept) is near zero, and can be taken as zero with no significant error.

All of these are easy to implement in the display firmware, the third of these is a better fit and not much harder to calculate than the others.

So, for the range 2-200W, \(P=1.026\text{e-18} + 0.883 Vo+1.89 V_o^2\) is a good expression for conversion of Vo to Power.

Note that there are insufficient data points below 2W to be confident that this curve fit has good accuracy in that range. If we assume that it was good down to 1W, then with Pfwd=100W and Pref=1W, we have a lower limit for accurate VSWR measurement of 1.2 in that scenario. It would be sensible if the digital display did not show VSWR where Pref<1W (at least pending further measurement).

If we allow 5% error in measurement of each of Pfwd and Pref, then we should have low confidence in calculated VSWR greater than 40 and such values should not be displayed.

A work in progress..

]]>Let’s discuss what the term means, and the uncertainty of measurement of DUT VSWR or ReturnLoss due to coupler Directivity.

Consider the above diagram, when terminated in a matched load, the key performance characteristics are:

- Coupling Factor: Relates input power (at P1) and that delivered to the coupled port, P3;
- Directivity: This is a measure of the coupler’s ability to separate waves propagating in forward and reverse directions, as observed at the coupled (P3) and isolated (P4) ports;
- Isolation: Relates input power (at P1) and that delivered to the uncoupled port, P4; and
- Insertion Loss: This is the ratio of power in a matched load without and with the coupler inserted.

The values of these characteristics in dB are:

Coupling \(C = \frac{P1}{P3}\)

Directivity \(D = \frac{P3}{P4}\)

Isolation \(I = \frac{P1}{P4}\)

InsertionLoss \(L = \frac{P1}{P2}\)

Note that Directivity can be calculated from Coupling and Isolation: \(D = \frac{P3}{P4}=\frac{I}{C}\) .

These values are often expressed in dB by taking 10log of the value, but lets work in simple numeric ratios to explain the ‘problem’, we will graduate to dB a little later.

Let’s say we have a coupler with Directivity=1000, then for 1V in the Coupled Port P3 from the forward wave, there will be \(\sqrt{\frac{1}{1000}}=0.032 \text{ V}\) at some unspecified phase in the Isolated Port P4.

So, lets say we have a DUT with VSWR=1.5, ReturnLoss=14.0dB or 25, so that causes a voltage of \(\sqrt{\frac{1}{25}}=0.2 \text{ V}\) at some unspecified phase in the Isolated Port P4.

So. the superposition of both voltages with unknown phase relationship will have a magnitude between \(0.2-0.032=0.18 \text{ V}\) and \(0.2+0.032=0.23 \text{ V}\). The Directivity of the coupler is a measure of its imperfection and it gives rise to error in the measured result, albeit moderate small in this case. In fact, displayed VSWR will be somewhere in the range 1.4 and 1.6.

That range might seem pretty acceptable, but if you tried to measure a DUT with VSWR=1.1 with the same coupler, the results are poorer.

Above, the VSWR result would range from 1.03 to 1.17 (depending on the relative phase of the two components).

For some applications, the phase error might be important, eg it may be used to inform the algorithms of a auto-tune ATU.

As mentioned, the four performance parameters can be expressed in dB:

Coupling \(C_{dB} = 10 log \frac{P1}{P3}\)

Directivity \(D_{dB} = 10 log \frac{P3}{P4}\)

Isolation \(I_{dB} = 10 log \frac{P1}{P4}\)

InsertionLoss \(L_{dB} = 10 log \frac{P1}{P2}\)

Note that Directivity can be calculated from Coupling and Isolation: \(D_{dB} =I_{dB}-C_{dB}\).

For any given value of VSWR or ReturnLoss, we can readily calculate the error on magnitude and phase of P4 wrt P3 given Directivity. Likewise, we can find the minimum value of Directivity that delivers given uncertainty of magnitude and phase P4 wrt P3.

Let’s look at two examples.

Let’s start with an assumed coupler Directivity of 30dB, and explore the VSWR uncertainty at VSWR=1.2 using Calculate uncertainty of ReturnLoss and VSWR given coupler directivity.

The range of VSWR indicated is from 1.13 to 1.38 for DUT VSWR=1.2. You can try different inputs to explore the effect and choose a minimum Directivity to suit your applications needs.

In this case, the amplitude and phase errors are important, typically the algorithm at least in part does a binary search for a solution that meets a threshold VSWR value, and inputs to that process are both the magnitude and phase of P4 wrt P3.

Let’s start with an assumed coupler Directivity of 30dB, and explore the VSWR uncertainty at VSWR=1.5 (the tune intended tune threshold) using Calculate uncertainty of ReturnLoss and VSWR given coupler directivity.

This delivers a VSWR range of 1.40 to 1.60 which might be quite fine for the purpose, but we also need to look at the phase error as that may inform the tuning algorithm and phase error much more than 10° is likely to result in tune failures when the ‘wrong turn’ is taken. In this case, the phase error is just below 10°, so probably acceptable and worth testing a prototype not so much to see if it works, but if it fails very often when it should have worked.

- Directivity is a key performance parameter of a directional coupler.
- Whilst there are lots of published ham designs for directional couplers, it is rare to see published Directivity measurements.

This type of balun, properly implemented, is a good voltage balun, and it is quite suited to a highly symmetric antenna.

A good voltage balun will deliver **approximately equal voltages** (wrt the input ground) with **approximately opposite phase**, irrespective of the load impedance (including symmetry).

**Where the load is symmetric**, we can say a good voltage balun will deliver **approximately equal currents** with **approximately opposite phase**, irrespective of the load impedance.

It is an interesting application, and contrary to the initial responses on social media, there is a simple solution.

Let’s take a half wave dipole and lengthen it a little so the feed point admittance becomes 1/200-jB (or 200 || jX). We will build an NEC model of the thing in free space.

Above is a sweep of the dipole which is 3.14m long (we will talk about how we came to that length later), and the Smith chart prime centre is 200+j0… the target impedance.

Note here that at 45.4MHz, the feed point impedance is 72Ω.

Above, spinning up to 50.2MHz, feed point impedance expressed as a parallel equivalent is 201||j203. So, if we shunt the feed point with 203Ω of capacitive reactance (15.6pF) we have impedance close to 200+j0.

So, the length was adjusted so that Rp=200Ω with some Xp>0 at the desired frequency.

Now in case you think that Smith charts MUST have a prime centre of 50Ω…

… there is the solution wrt 50Ω.

Now it is probably more convenient to make the dipole short and use a shunt inductive reactance… so let’s work that through.

This time on a 50Ω chart, the necessary shunt element is an inductive reactance of 119Ω which will yield a feed point impedance of about 200Ω. That could be provided by a small solenoid inductor, or a shorted transmission line stub (aka a hairpin or beta match).

Above is a Simsmith model based on the NEC model imported into element L, and a shunt inductance created by a hairpin of 3mm wire spaced 100mm (Zo=500Ω) and length 222mm.

Contrary to some expert opinions, there is a simple practical solution to the stated problem.

There are many ways, but a simple one if you have an analyser that can be OSL calibrated, or a VNA (eg NanoVNA) is to calibrate it to measure the impedance or admittance at the dipole centre.

Now sweep the frequency range of interest, and adjust the dipole length until the conductance at the desired frequency is 1/200S (equivalent parallel resistance component is 200Ω). Then connect the shunt matching element and adjust it so that susceptance is zero, or the parallel reactance component of impedance is extremely high.

Connect the feed line up in the normal working configuration with the 1:4 coax half wave balun, and the impedance looking into the coax should now be close to 50+jΩ at the desired frequency.

This can provide a simple solution for a rotatable dipole with good match to 50Ω line.

]]>End Fed Half Wave matching transformer – 80-20m described a EFHW transformer design with taps for nominal 1:36, 49, and 64 impedance ratios.

Keep in mind that this is a desk design of a transformer to come close to ideal broadband performance on a nominal 2400Ω load with low loss. Real antennas don’t offer an idealised load, but this is the first step in designing and applying a practical transformer.

The transformer comprises a 32t of 0.65mm enamelled copper winding on a Fair-rite 5943003801 core (FT240-43) ferrite core (the information is not applicable to an Amidon core), to be used as an autotransformer to step down a EFHW load impedance to around 50Ω. The winding layout is unconventional, most articles describing a similar transformer seem to have their root in a single flawed design, and they are usually published without meaningful credible measurement.

This article presents a model of the transformer using the 1:49 taps, and measurements used to calibrate the model.

See also On ferrite cored RF broadband transformers and leakage inductance.

Above is a pic of the prototype being measured with a 2400+j0Ω load in a 4t:28t connection. Sweeps of the transformer with OC and SC terminations were also made, and all three used to calibrate the Simsmith model.

Above is the calibrated Simsmith model with 65pF compensation capacitor added. The blue curves are the uncompensated VSWR and losses, and the magenta are with compensation. Note that the compensation capacitor is a high quality capacitor, eg silvered mica.

Optimal compensation capacitance on a real antenna may be a little different, pre prepared to measure and trim.

So, InsertionVSWR on a nominal 2400Ω load is less than 2.3 from 80m to 20m.

Core loss is highest at 20m, 0.36dB, which equates to 8.6W of core loss at 100W input.

Above, worst expected core temperature rise in free air is at 14MHz, about 51°.

Above, at 3.6MHz, expected core temperature rise in free air is a little lower at about 37°.

The core measured showed 35° in free air @ 100W through @ 3.6MHz suggesting it is probably best rated for no more than 300W continuous, perhaps less depending on the enclosure. These results are consistent with the measured impedance of the prototype, but it is wiser to use the model prediction of expected average characteristic of the cores.

]]>Before looking at the specifics of the Hirose U.FL connector, clean connectors work better and last longer. That should not be a revelation.

A can of IPA cleaner and a good air puffer are invaluable for cleaning connectors. The air puffer show has a valve in the right hand end, it doesn’t suck the dirt and solvent out of the connector and blow it back like most cheap Chinese puffers, this one was harder to find and expensive ($10!).

A clean tooth brush and / or small paint brush may prove useful. I would not put cotton buds, Q-tips or anything with free lint into the connector unless you are sure you can remove any lint (like with a strong jet of clean oil free compressed air).

The Hirose U.FL connector is widely used on miniature equipment for connecting RF coax cables.

I use them in lots of projects, mainly 2.4GHz WiFi and 915MHz LoRa. Above is an example where a 2.4GHz WiFi antenna is attached to an ESP8266 module in a project providing telemetry of dam level sensed with a 4-20mA pressure transducer.

The connector above has been on and off a development board more than 30 times, it is still in good working order. Visually, it cannot be faulted. The connector is on a Molex 105262 915MHz antenna which cost about $6 a few years ago, it is inexpensive hardware, but good quality.

If you take care of quality connectors they last more than 30 cycles, but if you do not, they might not last 10 cycles.

Above is a close up of the U.FL connector, it has two ears for lifting it off the male part without cocking it sideways (which will damage the connector).

Above, a DIY tool hooked under the ears. It snuggly fits so it cannot disengage, and it does not prevent expansion of the spring rim which must expand to disengage the male part. Note that it does not apply force to the cable or its crimp.

Above, the other end of my DIY tool is ground flat and square to the shaft, and allows pressure to be applied to the connector whilst without allowing it to cock sideways (which will damage the connector). Note that it does not apply force to the cable or its crimp.

This tool can reach down into confined spaces, so there is almost never an excuse to not use it.

With all that, IMHO opinion the use of U.FL connectors on boards like that above does not make a lot of sense for several reasons, but if you have one, and take care with the connectors as discussed above, you should get good value from the thing.

]]>90° methodas I will call it.

The reason why people make measurements at +/- 90 degrees on the smith chart is because the measurement accuracy using the shunt configuration when trying to measure the nominal value of an inductor or capacitor is highest at 0+j50 ohms (or 0-j50 ohms… OD).

To be clear, this is the phase of s11 or Γ being + or – 90° as applicable.

Is there something optimal when phase of s11 is + or – 90°?

Does the software / firmware / hardware give significantly more accurate response under such a termination?

Above is a diagram from a HP publication, slightly altered to suit the discussion.

V1 and V2 denote points of measurement proportional to the forward wave and reflected wave, think of uncorrected \(s_{11} \propto \frac{V_2}{V_1}\). Remember that s11 is a complex quantity, having amplitude and phase.

Different circuits and test configurations mean that the propagation time from the V1 sensor via the directional coupler to the terminals (shown as small circles) and connecting wires to the component Zx, reflection back along the path to the directional coupler and then to the V2 sensor is significant. That propagation time is manifest as a phase delay proportional to frequency.

Realise that |V1| will usually be relatively high, but |V2| may be very low, usability limited by the noise floor. Some detector circuits have weaknesses in phase measurement, more so when V2 is weak.

Above is a plot of the uncorrected phase of s11 from a NanoVNA with a SDR-kits test board OC termination and connected by about 300mm of RG400 coax to the NanoVNA.

In this case, |s11| is very close to unity, as it would be for measuring a high Q inductor or capacitor. Note there are no apparent glitches or even obvious noise on the measurement. There is no evidence of a range of phase of uncorrected s11 that should be avoided for accuracy reasons.

Now after calibration and application of correction, the phase of s11 above becomes approximately zero though the calibration frequency range.

If you were to connect a capacitor and find a frequency where the indicated phase of s11 is 90°, realise that the phase difference V2/V1 is larger, for example if that frequency was 50MHz, the phase of V2/V1 would actually be 90+63=153°.

So, what is the magic of displayed \(\angle s_{11}=90 °\)?

Why would you restrict the instrument to measure equivalent inductance at only one frequency that might not be relevant to the application (equivalent series inductance is not a frequency independent characteristic)?

In any event, the phase angle of the raw forward and reflected signals as sensed is likely to be significantly different to a corrected display and attempts to optimise the phase angle actually sensed is incredibly naive.

]]>There are occasions where it is not possible, or not convenient to locate the DUT at the reference plane. This article discusses the problem created, and some solutions that might give acceptable accuracy for the application at hand.

The discussion assumes the VNA is calibrated for nominal 50+j0Ω.

Above is a diagram of a configuration where the unknown Zl is not located exactly at the reference plane, but at some extension.

The problem created is that Vr50’/Vi50′ (s11) is not the same as if Zl was attached directly at the reference plane.

Let’s look at some possible solutions.

If the extension can be well characterised as a uniform transmission line, we can estimate the effect of the extension by calculation and approximately correct it.

The impedance transformation due to a section of uniform transmission line is \(Z_{in}=Z_0 \frac{Z_l+Z_0 tanh(\gamma l)}{Z_0+Z_l tanh(\gamma l)}\). If the transmission line parameters are known, the the impedance ‘measured’ at the reference plane can be corrected to the actual DUT location.

This is not a common feature, but it appears in Rigexpert’s Antscope (1) as the add/subtract cable feature.

The accuracy depends on the accuracy of the transmission line model and the line characterisation, it needs to be verified, it is not an insignificant issue.

If we can assume that port extension conductors form a uniform transmission line with negligible loss, we can use the relationship that \(Z_{in}=Z_0 \frac{Z_l+\jmath Z_0 tan(\beta l)}{Z_0+\jmath Z_l tan(\beta l)}\).

We can correct the measurement by adjusting for the extension round trip phase delay due to βl, so at each measurement frequency we add that phase delay back into the phase of ‘measured’ s11.

Accuracy depends on Zo=50+j0Ω and negligible loss, though acceptable results might be obtained for small departures. Note that negligible loss infers a short line section.

This facility is often provided in VNAs and PC client programs.

This can also be used with good effect to approximately compensate for a test fixture that does not exactly meet the conditions specified previously. The error may be small if:

- the line section is electrically very short; and
- Zl >>Zo; or
- Zl<<Zo.

If we assume that port extension conductors form a uniform transmission line with negligible loss, we can use the relationship that \(Z_{in}=Z_0 \frac{Z_l+\jmath Z_0 tan(\beta l)}{Z_0+\jmath Z_l tan(\beta l)}\).

Let’s look in more detail at the two cases.

\(Z_{in}=Z_0 \frac{Z_l+\jmath Z_0 tan(\beta l)}{Z_0+\jmath Z_l tan(\beta l)}\). \(For Z_l>>Z_0, Z_{in} \to Z_0 \frac{1}{\jmath tan(\beta l)}\) so we can derive an equivalent length at Zo: \(Z_{0_1} \frac{1}{tan(\beta_1 l_1)} \approx Z_{0_2} \frac{1}{tan(\beta_2 l_2)}\).

For small values of \(\beta l, tan(\beta l)=\beta l\), and noting that \(\frac{\beta_1}{\beta_2}=\frac{v_{f2}}{v_{f1}}\) (where vf is the velocity factor), \(l_2 \approx \frac{Z_{0_2}v_{f2}}{Z_{0_1}v_{f1}}l_1\).

To calculate e-delay, Z_{02} and v_{2} will be 50 and 1 respectively, and \(edelay=\frac{l}{c_0 v_f}=\frac{l \cdot \text{1e12}}{299792458} \text{ps}\).

So, it turns out that when Zl dominates the expression for Zin, that an electrically short uniform transmission line port extension of some Zo other than 50Ω can be offset as in the expression above.

The appropriate e-delay (as it is often known) can be discovered by measurement of an OC at the end of the extension, and adjusting it until the phase of s11 is 0° independent of frequency.

Whilst the assumptions might seem quite restrictive, this technique can be used with good utility for suitable DUT and fixture, eg finding the high impedance self resonant frequency of an inductor / resonator.

\(Z_{in}=Z_0 \frac{Z_l+\jmath Z_0 tan(\beta l)}{Z_0+\jmath Z_l tan(\beta l)}\). \(For Z_l<<Z_0, Z_{in} \to Z_0 \jmath tan(\beta l)\) so we can derive an equivalent length at Zo: \(Z_{0_1} tan(\beta_1 l_1) \approx Z_{0_2} tan(\beta_2 l_2)\).

For small values of \(\beta l, tan(\beta l)=\beta l\), and noting that \(\frac{\beta_1}{\beta_2}=\frac{v_{f2}}{v_{f1}}\) (where vf is the velocity factor), \(l_2 \approx \frac{Z_{0_1}v_{f2}}{Z_{0_2}v_{f1}}l_1\).

To calculate e-delay, Z_{02} and v_{2} will be 50 and 1 respectively, and \(edelay=\frac{l}{c_0 v_f}=\frac{l \cdot \text{1e12}}{299792458} \text{ps}\).

So, it turns out that when Zo dominates the expression for Zin, that an electrically short uniform transmission line port extension of some Zo other than 50Ω can be offset as in the expression above.

The appropriate e-delay (as it is often known) can be discovered by measurement of an SC at the end of the extension, and adjusting it until the phase of s11 is 180° independent of frequency (easiest with a wrapped phase plot if available).

Whilst the assumptions might seem quite restrictive, this technique can be used with good utility for suitable DUT and fixture, eg finding the low impedance resonant frequency and input impedance of a transmission line section.

]]>