PllLdr application - Si4133G (VK3XDK Agile PLL)

This article describes an application of PllLdr to an Si3133G PLL.

Fig 1:

Fig 1 shows the target PLL board, a VK3XDK AgilePLL. The PICAXE chip on the AgilePLL has been removed (with some difficulty due to the DIP switch location) and a DIP header plug used to connect a prototype PllLdr to the board. A 3.3K resistor has been connected from the AUXOUT pin (lower right) to pin 8 of the DIP socket (unused in the original). This connects the AUXOUT (used for LDETB) to the PllLdr and isolates it sufficiently to allow ISP to work on the PllLdr.

Fig 2:

Fig 2 shows the prototype PllLdr module. The 10way ribbon cable from the left is for ISP, and connects via a 10/6pin adapter to the on board 6pin ISP header. The header and shunts to the left are for frequency selection. The on-board pull-ups won't hurt, but aren't needed. The cable to the right is to the DIP header plug on the AgilePLL.

Fig 3:

Fig 3 shows the UsbASP programmer, which has been modified so that it does not supply power to the target and it operates at 3.3V for compatibility with the target.

Characteristics of the Si4133G

The Si4133G has three PLLs, RF1 and RF2 share a single output port so only one can be used at a time, and another designated IF.

Fig 4:

The stated range of centre frequencies (CF) supported are given in the datasheet as shown in Fig 4. The centre frequency is determined by the internal inductance and capacitance and the external inductor. This does not imply the VCO lock range.

When a device is built with a particular value of inductor, it has a certain range over which the VCO can be controlled, and that range is found by measurement as explained in AN31. This represents the range of frequencies that the VCO can lock at at the given temperature, voltage etc. The lock range with variation in temperature, voltage etc will be reduced somewhat.

The Si4133 datasheet describes the process: 

Self-Tuning Algorithm

The self-tuning algorithm is initiated immediately after powerup of a PLL or, if the PLL is already powered, after a change in its programmed output frequency. This algorithm attempts to tune the VCO so that its freerunning frequency is near the desired output frequency. In doing so, the algorithm compensates for manufacturing tolerance errors in the value of the external inductance connected to the VCO. It also reduces the frequency error for which the PLL must correct to get the precise desired output frequency. The self-tuning algorithm will leave the VCO oscillating at a frequency in error by less than 1% of the required
output frequency.

After self-tuning, the PLL controls the VCO oscillation frequency. The PLL will complete frequency locking, eliminating any remaining frequency error. Thereafter, it will maintain frequency-lock and compensates for effects from temperature and supply voltage variations.

The Si4133G’s self-tuning algorithm compensates for component value errors at any temperature within the specified temperature range. However, the ability of the PLL to compensate for drift in component values that occur after self-tuning is limited. For external inductances with temperature coefficients approximately ±150 ppm/°C, the PLL can maintain lock for changes in temperature of approximately ±30°C.

Applications in which the PLL is regularly powered down (such as GSM) or switched between channels can minimize or eliminate the effects of temperature drift because the VCO is re-tuned when it is powered up or when a new frequency is programmed. Applications in which the ambient temperature can drift substantially after self-tuning, it might be necessary to monitor the LDETB (lock-detect bar) signal on the AUXOUT pin to determine the locking state of the PLL. See "Auxiliary Output (AUXOUT)" on page 18 for how to select LDETB.

So, after locking, the ability of the PLL to compensate for changes in VCO components with temperature etc is limited to about ±0.5%, but if the Self Tuning process is re-driven, the available lock range is much greater. The LDETB signal can provide the cue to the external circuit to re-drive the Self Tuning process.


Configuration data for the PllLdr is held entirely in EEPROM. In the following tests, different EEPROM images are created using an online generator at MCU to load PLL configuration registers. The EEPROM image when generated is downloaded to a workstation and loaded to the PllLdr AVR chip using the programmer shown in Fig 3.

Range of RF1 and RF2 VCOs

This test was to find the range of RF1 and RF2 VCOs using the procedure set out in AN31.



An EEPROM image with register settings for high and low frequencies for RF1 and RF2 was created.

The configuration was loaded and the range of each VCO observed at 20°:

The range is about ±15% about the geometric mean centre frequency (CF).

The AgilePLL was heated with a hair dryer and cooled with freeze spray, and the change in frequency noted. The variation in frequency was about ±6MHz at 1024MHz, or about ±0.6%. When that is allowed for, for reliability, the application should not use more than about ±13% of CF.

Nevertheless, SiLabs cautions against using more than ±5%:

Q: The PLL I am using has a tuning range larger than ±5%. Can I use this larger range in my application?
A: This is not recommended and should only be done after extensive experimentation. The ±5% tuning range
is designed to compensate for tuning inductor variations and provide sufficient margin for PCB manufacturing
process variations. Therefore, the tolerance of the tuning inductor should always be taken into account.
Ranges as large as ±12% have been observed during laboratory experiments. However, such large ranges
cannot be guaranteed due to concerns about changes in the operating conditions (temperature, supply
voltage, etc.) as well as the tolerance of the tuning inductor.

Where the tolerance of the inductor is eliminated by hand tuning, part of their allowance for inductor tolerance can be reallocated to operating range.  They state that they have included ±10% allowance for inductor tolerance, which translates to ±5% of frequency, so it may be quite sound to add that ±5% inductor tolerance back into their ±5% composite range to achieve ±10% working range where the inductor is trimmed to the desired CF.

Applying that logic to this particular board:

Temperature tolerance


The configuration above was loaded, setting the RF2 to 1296, and the board heated and cooled. It was observed that it was possible to cause the PLL to lose lock, and it did not restore until the extreme temperature dissipated. This behaviour was also observed using the standard AgilePLL controller. Although SiLabs expect that the VCO should be able to maintain lock over a range of ±30° based on an assumed temperature coefficient of external inductors, it is the actual circuit implementation that determines the capacity of the circuit to handle a range of temperatures.


The above configuration enabled LDETB monitoring in PllLdr, and it was observed that the AgilePLL relocked at extreme temperatures when the limit of control range was reached, so it was able to maintain lock over a wider operating temperature range.



Version Date Description
1.01 05/08/2012 Initial.

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