ADF4351 / PllLdr checkout

PllLdr is a generic microcontroller to load a PLL chip’s configuration registers using SPI. SPI is used by many PLL and DDS chips, data format and content varies from chip to chip.

This article documents checkout on an ADF4351 PLL chip. The ADF4351 is a wideband INT-N / FRAC-N synthesiser with integrated VCO, output covers 36-4400MHz (continuous).

The test was made on an inexpensive module purchased on eBay for about A$33 posted.


Above is the test frame. At the left is a PllLdr prototype running on 5V, then a 4 channel 5V/3.3V  level converter, the ADF4351 module and at the right a power supply board. The level converter is not needed if the PllLdr chip was run on 3.3V, it was used to test a ‘worst case’ scenario.


Above, a close up of the board.


As can be seen, the connectors are not designed for the 0.8mm PCB used, and the right hand connector has not been connected to the track. Chinese ‘quality’.

The onboard 25MHz crystal oscillator was used as the reference, but a 10MHz reference from a GPSDO could be used for high accuracy.

A configuration was worked up for 50.1MHz using AD’s configuration tool.

screenshot-15_09_16-07_57_26As can be seen, the configuration is quite complex and comprises 5 x 40bit registers.

Though the purpose of the test is primarily to test the SPI register load, the frequency has been chosen to ensure that the 1/64 output divider is used (ADF4350 does not have that division, and there are chips labelled ADF4351 coming out of China that do not have that division).

A json description of the data structure for PllLdr follows, only one slot is configured.

//EEPROM data file for AD4351
//test file: 50.1MHz

Registers are loaded MSB first (differently to a lot of other AD synthesiser chips), and R5 to R0 in sequence.


Above is a map of the EEPROM for this single register set test. EEPROM usage is 6+40*regsets, so a 512B EEPROM (ATTINY84) will accommodate 12 full register sets, 256B (ATTINY44) will accommodate 6 full register sets.


Above is a logic trace of the SPI burst (though the data here is different to that for the 50.1MHz example above). Total load time is about 250µs.

The output was observed on a SSB communications receiver at 50.1MHz, and the system operated reliably.