This article documents design of a capacitive transformerless power supply for operating low voltage, low power logic from power mains. The intended application is PAROT (Duffy 2013), though it has potentially wider application.
(Microchip 2004) gives a method for design of a capacitive transformerless power supply for operating low voltage, low power logic from power mains. The equations seem simplistic for a circuit whose apparent simplicity belies the complexity of an optimal design that properly tolerates supply voltage and load variations. For that reason, a SPICE simulation was used to refine a design.
The immediate application is for the PAROT chip driving a 40A SSR.
Above is measured characteristic of a Fotek 40A SSR, it seems typical of several similar types on hand. It appears that much smaller SSRs in the 2A range require fairly similar current.
Clearly there is an advantage in keeping the logic voltage low, this design will target 4V (though there is benefit in lower voltage).
The power supply then needs to supply around 15mA from minimum mains voltage taken to be 90% of 230Vrms (293Vpk) at 50Hz.
Above is the optimised simulation circuit. Larger R1 reduces inrush current, but degrades regulation. Larger C2 reduces ripple but at the expense of startup time.
Maximum dissipation occurs in R1 at maximum mains voltage, taken to be 358Vpk.
Above is the current in R1 at high mains voltage. Power dissipated in R1 will be 0.076^2/2*220=0.635W, a 1W resistor is selected for the prototype though 2W is probably justified for production.
Expected current drawn is about 50mA, apparent power about 12VA and power about 1W, PF<10% (leading).
A prototype was tested on a variable AC supply (isolation transformer and Variac). The zener used tested at 4.4V, so output voltage will be 0.3V lower than the model. R1 was 470/2Ω, and R2 was 470/2Ω. C1 was 3×0.22µF. C2 was 1000µ which roughly halves the ripple.
Output voltage was 3.8V, and was invariant from 200-260Vrms input. Ripple measured 0.05Vrms (almost invariant of input voltage in the above range), so 0.05*2*3^0.5=0.173Vpp which is 0.05/3.8=1.3%.
Temperature of components were checked at 260Vrms input, and were as expected, R1 being the hottest component by far with 13° rise.
As a test, C1 was reduced to 0.44µF. Output voltage fell and regulation was much poorer. This test validates the need for the larger capacitor.
Based on the prototype tests and (Motorola nd) discussion of transient power handling of the zener diode, a design with R1=100Ω was modelled and the inrush starting at AC cycle max is 3.6A for 0.03ms which is well within the withstand of a glass DO-35 500mW zener. The average dissipation in R1 is 0.07^2/2*100=245mW, a 1W metal film resistor provides adequate capacity.
Above is the revised SPICE model results at 205Vrms. Faster startup, lower dissipation, reduce power consumption.
Note: a full wave rectifier design was dismissed. For some intended applications, it is necessary that the -ve DC rail is connected to the mains Neutral, and that is not possible if a bridge rectifier is used.
- Duffy, O. March 2013. Power Amplifier Run On Timer (PAROT). http://owenduffy.net/module/parot/index.htm.
- Microchip. Aug 2004. Transformerless Power Supplies: Resistive and Capacitive AN954.
- Motorola. nd. AN784 Transient power capability of zener diodes Rev 1.
- OnSemi. Jun 2005. TVS/Zener Theory and Design Considerations HBD854/D.